1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to system LSI (Large Scale Integration) power consumption reduction.
2. Description of the Related Art
A technology called dual threshold voltage/power supply voltage (dual Vt/Vdd) has existed for some time as a design method that lowers the power consumption of an LSI. With this technology, design is carried out as follows.
For semiconductor elements that form a critical path, the threshold voltage (Vt) is lowered and the power supply voltage (Vdd) is raised. On the other hand, for semiconductor elements that do not form a critical path, the threshold voltage (Vt) is raised and the power supply voltage (Vdd) is lowered.
By means of the above design method, the LSI operating power consumption, subthreshold leakage current, and system LSI standby subthreshold leakage current, are all reduced. A concrete example of implementation of the above effects is given in claim 2 of Patent Document 1 (Japanese Patent Publication No. 3498641), for example. Also, Non-patent Document 1 (David Kung, et al., “Pushing ASIC Performance in a Power Envelope”, DAC 2003, Jun. 2, 2003) states that the technology described therein was applied to an actual LSI and had the effect of a 60 to 65% reduction in power consumption.
However, with conventional LSIs, there is a problem of not being able to provide for the incorporation into a single system LSI of functions that were divided among a plurality of LSIs. For example, with a process technology of 90 nm to 65 nm, several hundred thousand transistors (Trs) may be integrated in a single system LSI chip.
For example, a voice processing function, photographic image processing function (such as JPEG processing), and moving image processing function (such as MPEG2 processing) that were previously implemented by separate chips can now be implemented by a single system LSI.
FIG. 21 is a conceptual diagram showing an example of a system LSI chip incorporating a variety of functions in a single chip. In FIG. 21, the function blocks are assumed to be as follows, for example. Function blocks M1, M2, M3, and M4 are memory blocks such as SRAM, ROM, or DRAM. Function blocks A, B, C, D, and E are analog blocks such as A/D, D/A, and power supply circuits. Function blocks L1, L2, L3, L4, L5, L6, L7, and L8 are logic signal processing blocks such as voice processing function, photographic image processing function (for example, JPEG processing), and moving image processing function (for example, MPEG2 processing) blocks.
FIG. 22 comprises graphs showing examples of the relationship between path delay and count value for function blocks. The path delay value is shown on the horizontal axis, and the count value on the vertical axis. FIG. 22 (A) shows an example of a voice processing function block, FIG. 22 (B) an example of a photographic image processing (for example, JPEG processing) function block, and FIG. 22 (C) an example of a moving image processing (for example, MPEG2 processing) function block. As the necessary processing capability differs for a voice processing function, a photographic image processing function (for example, JPEG processing), and a moving image processing function (for example, MPEG2 processing) when path delay is shown on the horizontal axis and the count value on the vertical axis, the peak path delay values also differ as shown in FIG. 22 (A), FIG. 22 (B), and FIG. 22 (C).
Normally, the peak path delay value for each function block increases according to the function block in the order: voice processing function<photographic image processing function<moving image processing function.
Normally, assuming that a system LSI is run on a single system clock, the operating frequency at which the system LSI must operate is decided, and the necessary path delay values are decided.
In FIG. 22 (A), FIG. 22 (B), and FIG. 22 (C), the path delay value necessary for operation on a particular single clock is shown by a vertical line. A path that has a value greater than or equal to the path delay value necessary for operation on this particular single clock is a critical path. As can be seen from FIG. 22 (A), FIG. 22 (B), and FIG. 22 (C), the critical path varies somewhat for different function blocks.
Patent Document 1 and Non-patent Document 1 do not disclose a configuration, method, and so forth for attempting to reduce the operating power consumption, subthreshold leakage current, and system LSI standby subthreshold leakage current, of a system LSI that has a plurality of function blocks whose peak path delay values differ.